During the formation of semiconductor devices, variations in diffusion pattern density can occur. That is, the diffusion or active regions typically disposed in n-type or p-type wells may not be evenly spaced about the semiconductor substrate. Such uneven spacing of the diffusion or active regions causes variations in planarization rates. More specifically, diffusion regions are commonly covered by nitride which acts as a stop during subsequent planarization steps. Thus, during, for example, chemical mechanical polishing or resist etch back steps, the planarization process etches or polishes through overlying layers such as, for example, an oxide layer until the underlying nitride layer is reached. When nitride covered diffusion regions are separated by large distances, areas disposed between the nitride covered diffusion regions may be etched or polished more deeply than the areas disposed directly above the nitride covered diffusion regions. Such a condition is commonly referred to as dishing or cusping. Similarly, when an uneven diffusion pattern density exists, oxide may deleteriously remain on the nitride layer after planarization steps. In order to prevent such planarization problems, fill pattern diffusion regions or "dummy diffusion patterns" are sometimes formed into the semiconductor substrate. The fill pattern diffusion regions are not used to form active semiconductor devices, but are, instead used to achieve a more even or consistent diffusion pattern density. Unfortunately, conventional fill pattern diffusion region locating methods have significant drawbacks associated therewith.
With reference now to Prior Art FIG. 1A, a schematic top plan view of a portion 10 of a semiconductor substrate having an active diffusion region 12 disposed within an n-type well 13, and another active diffusion region 14 disposed within a p-type well 15 is shown. Although such conductivity types are recited for wells 13 and 15 of the present embodiment, the present invention is also well suited to use with various of combinations of wells of either n-type or p-type doping. In Prior Art FIG. 1A, diffusion regions 12 and 14 are separated by oxide 16. Oxide 16 is formed or deposited into the semiconductor substrate by, for example, a shallow trench isolation process. It will be understood that during various processing steps, active diffusion regions 12 and 14 within wells 13 and 15, respectively, are covered by a layer of nitride. As shown in Prior Art FIG. 1A, portion 10 of the semiconductor substrate is not consistently or evenly covered by diffusion regions. For example, portion 10 of the semiconductor substrate has large open field areas between and surrounding active diffusion regions 12 and 14.
Referring next to Prior Art FIG. 1B, another schematic top plan view of portion 10 of a semiconductor substrate is shown. In Prior Art FIG. 1B, fill pattern diffusion regions or dummy diffusion regions, typically shown as 18, are formed into the semiconductor substrate. Typically, fill pattern diffusion regions 18 are disposed throughout portion 10 in order to achieve an even or more consistent diffusion pattern density thereon. It will further be noted, that fill pattern diffusion regions 18 are also disposed within n-type well 13 and p-type well 15. As with active diffusion regions 12 and 14, it will be understood that during various processing steps, fill pattern diffusion regions 18 are covered by a layer of nitride.
Referring now to FIG. 1C, another schematic top plan view of portion 10 of a semiconductor substrate is shown. In Prior Art FIG. 1C, a polysilicon interconnect line 20 is shown formed over at least one of fill pattern diffusion regions 18. Although fill pattern diffusion regions 18 are intended to improve semiconductor manufacturability processes, conventional fill pattern diffusion region placement methods have severe disadvantages associated therewith. Namely, parasitic capacitance is dramatically increased by having a polysilicon line disposed over fill pattern diffusion regions. Thus, polysilicon line 20 will experience substantial parasitic capacitance by virtue of being disposed over fill pattern diffusion regions 18. This parasitic capacitance results in slower signal line speeds due to RC (resistance-capacitance) effects. Unfortunately, conventional fill pattern generator and layout editor systems frequently locate fill pattern diffusion regions within, for example, wells 13 and 15, such that they underlie polysilicon interconnect lines.
With reference next to Prior Art FIG. 2, a side sectional view of portion 10 of Prior Art FIG. 1C taken along line A--A is shown. Polysilicon interconnect line 20 is separated from fill pattern diffusion region 18 by only a thin gate oxide layer 22. Typically, gate oxide layer 22 has a thickness, t, in the range of approximately 40-80 angstroms. Capacitance, C, experienced by polysilicon line 20 is given by the equation, C=.epsilon.A/d, where A is the area of the conductive portions separated by dielectric gate oxide 22, .epsilon. is the dielectric constant of gate oxide 22, and d is the thickness, t, of gate oxide layer 22. Because the value, d, (i.e. the thickness of the dielectric layer) is in the denominator, with all other values unchanged, the thinner the dielectric layer (i.e. the smaller the value of d), the greater the parasitic capacitance. Thus, it is desirable to have polysilicon line 20 disposed over a dielectric having a greater depth. Therefore, it is desirable to have polysilicon line 20 disposed over trench oxide regions 16 rather than over fill pattern diffusion regions 18.
In one prior art attempt to reduce parasitic capacitance, fill pattern diffusion regions have been "hand-placed" on the semiconductor substrate. Such a prior art method is extremely time-consuming, labor-intensive, and very impractical for large volume applications. For example, in ASIC (application specific integrated circuit) environments, numerous circuit designs may be designed and implemented in relatively short periods of time. In such ASIC environments, hand-placing of fill pattern diffusion regions onto various semiconductor substrates having differing design and layout is not a viable solution.
Thus, a need exists for method to locate fill pattern diffusion regions on a semiconductor such that the fill pattern diffusion regions do not underlie polysilicon interconnect lines. Still another need exists for a method to locate fill pattern diffusion regions such that the fill pattern diffusion regions do not underlie polysilicon interconnect lines wherein the method is automated. Yet another need exists for a method to locate fill pattern diffusion regions on a semiconductor substrate wherein the method can be used with conventional layout editors or fill pattern generation systems.